RADIOPRIMEMNOE DEVICE COHERENT RADAR WITH OPTIMAL FILTERING OF SIGNAL

摘要

u0440u0430u0434u0438u043eu043fu0440u0438u0435u043cu043du043eu0435 coherent radar device with optimal filtering the signal with the first analog to digital converter, the first and second mixers often t, the first n - u0440u0430u0437u0440u00a0u0434u043du044bu0439 u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0438u0439 adder, first and second comparator organizations u043du0430u043fu0440u00a0u0436u0435u043du0438u00a0, u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 so that the first channel is u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e reception device the phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 pretreatment device a1 and a3.the device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 channel contains a first adder, a temporary u0443u0441u0438u043bu0435u043du0438u00a0 amplifiers with automatic adjustment the first and second mixers and frequency, the first and second operational amplifiers, first and second comparator organizations u043du0430u043fu0440u00a0u0436u0435u043du0438u0439, first and second filters a low frequency, the first and the second u0438u043du0442u0435u0433u0440u0430u0442u043eu0440u044b, first and second circuits u043au043eu043du0442u0440u043eu043bu00a0,the u0444u043eu0440u043cu0438u0440u043eu0432u0430u043du0438u00a0 signal servicing, in turn, pretreatment device a3 first channel consists of the first and second analog digital surmounted u0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0, first and second u0446u0438u0444u0440u043eu0430u043du0430u043bu043eu0433u043eu0432u044bu0445 transducers, devices of digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0, u043fu043eu0441u0442u043eu00a0u043du043du043eu0433u043e storage device numbers u043eu0432u043eu0433u043e u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0, first and second reverse metersthe first and second accumulating n - u0440u0430u0437u0440u00a0u0434u043du044bu0445 u0441u0443u043cu043cu0430u0442u043eu0440u043eu0432, first and second add drop multiplexers, u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 address records, the first and second operational u0437u0430u043fu043eu043cu0438u043du0430u044eu0449 their devices through the u043fu0435u0440u0438u043eu0434u043du043eu0439 processing, u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 addresses u0447u0442u0435u043du0438u00a0, first and second optimal filters, u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 reference signals, the first and second icri u043eu0441u0445u0435u043c FiFo "first in, first out", the device u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0,the first and second switches, and a second channel contains a device for u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 and a provisional u043eu0431u0440u0430u0431u043eu0442u043a and the a4, which u0441u0445u0435u043cu043du043e - is made similar to the u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel and the provisional u043eu0431u0440u0430u0431u043eu0442 kee a3 first channel, and also includes first and second u0434u0435u0448u0438u0444u0440u0430u0442u043eu0440u044b,crystal oscillator, a frequency divider, u0443u0440u043eu0432u043du00a0, band pass filter, u0434u0438u0444u0444u0435u0440u0435u043du0446u0438u0440u0443u044eu0449u0430u00a0 chain, u0438u043du0442u0435u0433u0440u0438u0440u0443u044eu0449u0430u00a0 circuit, first and second resonant whiskers u0438u043bu0438u0442u0435u043bu0438, third and fourth add and synchronizer signals, and the receiver on the first channel is connected with the first gate device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e the phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 of the first channel.the first device output u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel is connected with the second front pretreatment device a3 first channel the first device output preprocessing the first channel is connected with the first gate a3 third u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, exit is connected to the third u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 connector output signal real u0441u043eu0441u0442u0430u0432u043bu00a0u044eu0449u0435u0439,the plug is connected with the input reference signal in frequency and u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0 u0443u0440u043eu0432u043du00a0 u0434u0435u043bu0438u0442u0435u043bu00a0 entrance, exit is connected with a long u0434u0435u043bu0438u0442u0435u043bu00a0 frequency filter the filter is connected with the entrance, exit long u0434u0438u0444u0444u0435u0440u0435u043du0446u0438u0440u0443u044eu0449u0435u0439 chain and an integrating chain way u0434u0438u0444u0444u0435u0440u0435u043du0446u0438u0440u0443u044eu0449u0435u0439 chain is connected with the entrance of the first r u0435u0437u043eu043du0430u043du0441u043du043eu0433u043e u0443u0441u0438u043bu0438u0442u0435u043bu00a0,the first output is connected to the second resonance u0443u0441u0438u043bu0438u0442u0435u043bu00a0 entrance device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 of the first channel, the second one the first resonance the main u0443u0441u0438u043bu0438u0442u0438u00a0 is connected with the second gate device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel, a chain is connected with the entrance u0432u0442u043eu0440u043eu0433 integrates on the resonance u0443u0441u0438u043bu0438u0442u0435u043bu00a0,the first output is connected to the second resonance u0443u0441u0438u043bu0438u0442u0435u043bu00a0 third entrance device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 of the first channel, the second one second r u0435u0437u043eu043du0430u043du0441u043du043eu0433u043e u0443u0441u0438u043bu0438u0442u0435u043bu00a0 is connected with the third gate device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel.the first device output u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel is connected to the second gate of the second channel preprocessing a4 a first device output pretreatment a4 second channel connected to the second gate fourth u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, exit the fourth u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 u0441u043eu0435u0434 ihnen with connector output signal u0441u043eu0441u0442u0430u0432u043bu00a0u044eu0449u0435u0439 delusions.the first output is connected to the entrance of the quartz synchronizer signal generator, the generator is connected with the fourth entrance exit quartz device grid u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 of the first channel, the second way is connected with the fourth front quartz generator device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043d u0438u00a0 a2 the second channel.the second output signal is connected to the first u0434u0435u0448u0438u0444u0440u0430u0442u043eu0440u0430 synchronizer entrance, exit is connected to the first u0434u0435u0448u0438u0444u0440u0430u0442u043eu0440u0430 u043fu00a0u0442u044bu043c entrance device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel, the third way is connected with the second u0434u0435u0448u0438u0444u0440u0430u0442u043eu0440u0430 synchronizer signals the entrance, exit is connected to the second u0434u0435u0448u0438u0444u0440u0430u0442u043eu0440u0430 u043fu00a0u0442u044bu043c entrance the device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel.solution u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0 u0443u0440u043eu0432u043du00a0 is connected with the first gate synchronizer signal, the second output device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel the third gate is connected with a synchronizer device output signals, the third phase u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel is connected with the third entrance mouth u0440u043eu0439u0441u0442u0432u0430 pretreatment a4 second channelthe second output device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel is connected to the second gate signal synchronizer, the third device output u043au0432u0430u0434 u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel is connected with the third front pretreatment device a3 first channelu043fu00a0u0442u044bu0439 way synchronizer signals is connected with the fourth front pretreatment device a4, the second channel, the sixth output signals with synchronizer u0435u0434u0438u043du0435u043d with u043fu00a0u0442u044bu043c entrance device pretreatment a4, the second channel, the seventh gate synchronizer signals connected with the sixth entry of the provisional a4 large processing of the second channel.eighth way synchronizer signals connected to the seventh door device pretreatment a4 second channel, u0434u0435u0432u00a0u0442u044bu0439 way synchronizer signal u043eu0435u0434u0438u043du0435u043d eighth entrance device pretreatment a4 second channel, u0434u0435u0441u00a0u0442u044bu0439 way synchronizer signals connected to the u0434u0435u0432u00a0u0442u044bu043c before entrance device provisional processing a4 second channelthe synchronizer output signals is connected with the contact impulse u0434u043bu00a0 u0444u043eu0440u043cu0438u0440u043eu0432u0430u043du0438u00a0 strobe adjustment of antenna, the output u0441u0438u0433u043du0430u043bu043e synchronizer in is connected to a contact signal launch u043eu043au043eu043du0435u0447u043du043eu0439 level transmitter, the output signal is connected to a contact signal synchronizer u043eu043fu0440u0435u0434u0435u043bu00a0u044eu0449u0435u0433u043e u0434u043bu0438u0442 u0435u043bu044cu043du043eu0441u0442u044c launch pulse transmitterthe fourteenth output synchronizer signals is connected to a contact signal u043eu043fu0440u0435u0434u0435u043bu00a0u044eu0449u0435u0433u043e launch phase pulse transmitter, u043fu00a0u0442u043du0430u0434u0446u0430u0442u044bu0439 way synchronizer sig. u043du0430u043bu043eu0432 is connected with the contact of the signal pulse u0431u043bu0430u043du043au0438u0440u043eu0432u0430u043du0438u00a0 receiver to output signals is connected with the contact of the accompanying pulse synchronizer the main signal.the seventeenth out synchronizer signals is connected to the contact of the transfer pulse, the eighteenth out synchronizer signals connected to the u0434u0435u0441u00a0u0442u044bu043c entrance the pre-processing device a4, the second channel, u0434u0435u0432u00a0u0442u043du0430u0434u0446u0430u0442u044bu0439 way synchronizer signals is connected with the third entrance in the third u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 and third in the fourth u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430,the synchronizer output signals is connected with the fourth front pretreatment device a3 in the first channel, the twenty first time synchronizer a signal is connected to the u043fu00a0u0442u044bu043c entrance device pretreatment a3 first channel, the twenty second output synchronizer signals is connected to the sixth gate the pre-processing device a3 first channelthe twenty third way synchronizer signals connected to the seventh door device pretreatment a3 first channel, the twenty fourth out sync u0438u0437u0430u0442u043eu0440u0430 signals is connected to the eighth entry device pretreatment a3 first channel, twenty u043fu00a0u0442u044bu0439 output signals connected to the u0434u0435u0432u00a0u0442 synchronizer ies a pre-treatment device a3 first channelthe twenty sixth synchronizer output signals connected to the u0434u0435u0441u00a0u0442u044bu043c entrance device pretreatment a3 first channel, parallel and pipeline connector u043du0444u043eu0440u043cu0430u0446u0438u0438 is connected with the first and eleventh entrances pretreatment device a3 in the first channel, the first and eleventh entrances hardware store u043bu044cu043du043eu0439 processing a4 second channeland with the fourth output synchronizer signal, the second output device is connected to the first channel preprocessing a3 first entering the fourth u043cu0443u043bu044cu0442u0438u043fu043bu0435 the acorn, the second device output pretreatment a4 second channel connected with the entrance of the third u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430,in the device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel first entrance is connected with the first gate u0441u0443u043cu043cu0430u0442u043eu0440u0430, exit is connected to the first gate u0441u0443u043cu043cu0430u0442u043eu0440u0430 blo amplifiers with a temporary automatic adjustment u0443u0441u0438u043bu0435u043du0438u00a0, exit block amplifiers with the automatic adjustment u0443u0441u0438u043bu0435u043du0438u00a0 is connected with the first u0432u0445u043eu0434u043e m the first u0441u043cu0435u0441u0438u0442u0435u043bu00a0 frequencies and with the first entrance of the second u0441u043cu0435u0441u0438u0442u0435u043bu00a0 frequenciessolution a first u0441u043cu0435u0441u0438u0442u0435u043bu00a0 frequencies is connected to the first entrance of the first operating u0443u0441u0438u043bu0438u0442u0435u043bu00a0, exit the first operational u0443u0441u0438u043bu0438u0442u0435u043bu00a0 is connected to the front of the first filter a low frequency, a first filter for low frequencies is connected to the first access device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 with the first channel, entrance two schemes u043au043eu043du0442u0440u043eu043bu00a0 and entering the first integrator.solution a first integrator is connected to the entrance of the first comparator u043du0430u043fu0440u00a0u0436u0435u043du0438u0439, exit the first comparator is connected to the second gate u043du0430u043fu0440u00a0u0436u0435u043du0438u0439 first u043eu043fu0435u0440u0430u0446u0438u043eu043du043du043eu0433 on the u0443u0441u0438u043bu0438u0442u0435u043bu00a0, exit the second u0441u043cu0435u0441u0438u0442u0435u043bu00a0 frequencies is connected to the first entrance of the second operating u0443u0441u0438u043bu0438u0442u0435u043bu00a0, exit the second operating u0443u0441u0438u043bu0438u0442u0435u043bu00a0 is connected with entrance w u043eu0440u043eu0433u043e filter low frequencya low frequency filter is connected to the third output device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel, with the entrance of the second scheme u043au043eu043du0442u0440u043eu043bu00a0 and bx odom's second integrator, a second integrator is connected to the second comparator u043du0430u043fu0440u00a0u0436u0435u043du0438u0439 entrance, exit the second comparator is connected to the second u043du0430u043fu0440u00a0u0436u0435u043du0438u0439 bx odom's second operational u0443u0441u0438u043bu0438u0442u0435u043bu00a0,the output of the first circuit is connected to the first u043au043eu043du0442u0440u043eu043bu00a0 entrance scheme u0444u043eu0440u043cu0438u0440u043eu0432u0430u043du0438u00a0 signal slope, a second circuit is connected to the second gate pattern forming u043au043eu043du0442u0440u043eu043bu00a0 u0432u0430u043du0438u00a0 signal slope, the output signal is connected to the second circuit u0444u043eu0440u043cu0438u0440u043eu0432u0430u043du0438u00a0 fixed access device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 of the first phase channelthe fourth input device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel is connected to the second gate u0441u0443u043cu043cu0430u0442u043eu0440u0430, the second input device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phases u043eu0432u043eu0433u043e u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel is connected with the entrance of the first u0441u043cu0435u0441u0438u0442u0435u043bu00a0 frequencies, a third input device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase a1 of the u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 the channel is connected to the second gate, second u0441u043cu0435u0441u0438u0442u0435u043bu00a0 frequenciesu043fu00a0u0442u044bu0439 entrance device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 the first channel is connected with the second entrance block amplifiers with automatic u0440u0435u0433u0443u043bu0438u0440u043eu0432u043au043e temporary in u0443u0441u0438u043bu0435u043du0438u00a0, plug input signal the second channel is connected to the first gate device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel.the first input device is connected to the first channel preprocessing a3 third entrance in the first u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, the second input device prior to the first channel is connected to the second processing space by the first analog to digital u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0, exit the first analogue to digital u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0 is connected with u043fu00a0u0442u044bu043c u0432u0445u043e digital home devices u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0,the first output device is connected to the first digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0 entrance the first n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430, first output the first n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e at u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430 is connected with the first entrance of the first u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, exit the first u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 is connected to the first gate u0443u0441u0442u0440u043e rapid storage u0439u0441u0442u0432u0430 through - u043fu0435u0440u0438u043eu0434u043du043eu0439 processing and the second entrance of the first switch.solution a first operational storage device through the u043fu0435u0440u0438u043eu0434u043du043eu0439 processing is connected to the first entrance of the optimal filter, the output of the optimal filter a first gate is connected to the first output of the first FiFo chips, chips FiFo is connected with the first switch in the first u043du0430u043fu0440u00a0u0436u0435u043du0438u0439,a first switch is connected to the first access device u043du0430u043fu0440u00a0u0436u0435u043du0438u0439 pretreatment a3 first channel, a third input device prior to the first channel is connected to first develop a3 in the second analog to digital u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0, exit the second analog to digital u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0 is connected with the second entrance device of digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0,the second output device of digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0 is connected with the first entrance of the second n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430, first exit the second n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e at u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430 is connected with the first entrance of the second u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430, exit the second u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 is connected to the first entrance of the second operational u0437u0430u043fu043eu043cu0438u043du0430u044eu0449u0435 the device through the u043fu0435u0440u0438u043eu0434u043du043eu0439 processing and the second entrance of the second switch.solution a second operational storage through the u043fu0435u0440u0438u043eu0434u043du043eu0439 processing is connected to a first gate of the optimal filter, a second u043eu043fu0442u0438u043cu0430u043bu044cu043du043eu0433 the filter is connected with the first entrance of the second chips FiFo, exit the second chips FiFo is connected through the first entrance of the second switch, a second switch u0441u043eu0435u0434u0438u043du0435 n to the second access device pretreatment a3 first channelthe second way the first n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430 is connected with the first entrance of the first reverse meter, a meter is connected through the first reverse with the entrance of the first u0446u0438u0444u0440u043eu0430u043du0430u043bu043eu0433u043eu0432u043eu0433u043e u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0, exit the first u0446u0438u0444u0440u043eu0430u043du0430u043bu043eu0433u043eu0432u043eu0433u043e u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0 is connected with the first entrance of the conversion analog to digital u0432u0430u0442u0435u043bu00a0,the second way the second n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430 is connected with the first entrance of the second reverse counter, the second counter is connected through a reverse with the entrance of the second u0446u0438u0444u0440u043eu0430u043du0430u043bu043eu0433u043eu0432u043eu0433u043e u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0, exit the second u0446u0438u0444u0440u043eu0430u043du0430u043bu043eu0433u043eu0432u043eu0433u043e u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0 is connected with a second front analog to digital u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0,the fourth input device a3 preprocessing first channel is connected to the entrance of the second analog to digital u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0, with a third door first wow analogue to digital u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u0442u0435u043bu00a0, with the first door device of digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0,u043fu00a0u0442u044bu0439 entrance device pretreatment a3 first channel is connected with the entrance u043fu043eu0441u0442u043eu00a0u043du043du043eu0433u043e digital storage device u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438 u00a0, first out u043fu043eu0441u0442u043eu00a0u043du043du043eu0433u043e storage device is connected to the third digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0 entrance device of digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0,the second way u043fu043eu0441u0442u043eu00a0u043du043du043eu0433u043e storage device is connected to the fourth digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0 entrance device of digital u0433u0435u0442u0435u0440u043eu0434u0438u043du0438u0440u043eu0432u0430u043du0438u00a0, sixth entrance the pre-processing device a3 first channel is connected with the second gate, second n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430 and second in the first n - u0440u0430u0437u0440u00a0u0434 the main u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430,the seventh gate device pretreatment a3 first channel is connected with the entrance of the second n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430 and with the third entrance pe u0440u0432u043eu0433u043e n - u0440u0430u0437u0440u00a0u0434u043du043eu0433u043e u043du0430u043au0430u043fu043bu0438u0432u0430u044eu0449u0435u0433u043e u0441u0443u043cu043cu0430u0442u043eu0440u0430, eighth input device a3 preprocessing first channel is connected with a second entrance to the second reverse u0447u0435u0442u0447u0438u043au0430, second by second u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430,with the entrance u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 addresses of record with the second entrance and the second entrance first u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430 first reverse meter, u0434u0435u0432u00a0u0442u044bu0439 provisional entry device the first channel is connected with a large processing a3 u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 addresses u0447u0442u0435u043du0438u00a0 entrance, entrance u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 reference signals with the second entrance of the second chips FiFo, with the entrance and the second entrance device u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 first chips FiFo,u0434u0435u0441u00a0u0442u044bu0439 entrance device pretreatment a3 first channel is connected with the first switch and the second entrance gate switch, first you the device is connected with the third u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 entrance first chips FiFo, second output device is connected with the fourth front u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 first chips FiFo,the third way is connected with the third gate device u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 second chips FiFo, fourth device output is connected with the fourth front u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 second icri u043eu0441u0445u0435u043cu044b FiFo, first out u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 reference signals is connected with the entrance of the optimal filter, the second output signal u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 united team don't with the second entrance second optimal filtersolution u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 address record is connected with the second storage device through the entrance of the first operational u043fu0435u0440u0438u043eu0434u043du043eu0439 processing and the second by second operating u0440u0430u0442u0438u0432u043du043eu0433u043e storage device through the u043fu0435u0440u0438u043eu0434u043du043eu0439 processingsolution u0444u043eu0440u043cu0438u0440u043eu0432u0430u0442u0435u043bu00a0 addresses u0447u0442u0435u043du0438u00a0 is connected with the third entrance first operational storage device through the u043fu0435u0440u0438u043eu0434u043du043eu0439 processing and the entrance of the second rapid storage device through the u043fu0435u0440u0438u043eu0434u043du043eu0439 processing, the input device of the first channel u043eu0431u0440u043eu0430u0431u043eu0442u043au0438 a3 is connected to the third the second u043cu0443u043bu044cu0442u0438u043fu043bu0435u043au0441u043eu0440u0430,u043cu0435u0436u043au0430u0441u043au0430u0434u043du044bu0435 u0441u0432u00a0u0437u0438 device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase u0434u0435u0442u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a2 the second channel are similar to u043cu0435u0436u043au0430u0441u043au0430u0434u043du044bu043c u0441u0432u00a0u0437u00a0u043c device u043au0432u0430u0434u0440u0430u0442u0443u0440u043du043eu0433u043e phase diet u0435u043au0442u0438u0440u043eu0432u0430u043du0438u00a0 a1 of the first channel, u043cu0435u0436u043au0430u0441u043au0430u0434u043du044bu0435 u0441u0432u00a0u0437u0438 pretreatment device a4 second channel are similar to u043cu0435u0436u043au0430u0441u043au0430u0434u043du044bu043c u0441u0432u00a0u0437u00a0u043c device store u043bu044cu043du043eu0439 a3 processing the first channel.