Memory chip with integral address scrambling unit whereby the address can be scrambled in different ways according to the address control bits

摘要

The memory chip has an integral address scrambling unit (22,23) which has address inputs for entering an address. The address scrambling unit is arranged and adapted such that the addresses can be scrambled differently dependent on the control bits. A memory cell field is provided and is connected to the output of the address scrambling unit. The scrambling unit may have several predefined scramblers for scrambling the addresses in different ways. Independent claims also cover a method of scrambling addresses.