Semiconductor memory device operating process, involves transferring write command to device synchronously with timing signal, and synchronously reading data with another timing signal while setting data validating signal

摘要

The process involves initializing two timing signals (CK, DK) and a data validating signal (DVLD), where the signal (DK) is independent from the signal (CK). The signal (DVLD) assumes two values when a data transfer to and from a memory device does not take place. A write command is transferred to the device synchronously with the signal (CK). Data (D0-D3) are read synchronously with the signal (DK) while setting the signal (DVLD). An independent claim is also included for a semiconductor memory device.