Circuit arrangement for monitoring address decoder e.g. for automotive engineering and vehicle dynamics, has first and second group decoder outputs supplied to double-rail checker

摘要

A monitoring circuit arrangement has input addresses decoded to output addresses via which address bits can be outputted and parity bits can be manipulated to the output addresses, where the decoder outputs are separated into even-numbered and odd-numbered decoder outputs, forming first and second groups together with OR-gates respectively. The decoder outputs of the first group and the decoder outputs of the second group are supplied to a first double-rail checker. An independent claim is included for a method for monitoring an address decoder.