首页> 外国专利> Gate structure with layered gate electrode stack comprising doped polysilicon layer and gate metal layer sandwiching barrier layer of metal nitride with metal contact film deposited on polysilicon layer

Gate structure with layered gate electrode stack comprising doped polysilicon layer and gate metal layer sandwiching barrier layer of metal nitride with metal contact film deposited on polysilicon layer

机译:具有分层的栅电极叠层的栅极结构,其包括掺杂的多晶硅层和将金属氮化物沉积在多晶硅层上的,将金属氮化物夹在中间的金属氮化物阻挡层的栅金属层

摘要

Gate structure (1) of transistor in semiconductor substrate (10) is formed by structuring layered gate electrode stack (1). On gate dielectric film (9) is deposited polysilicon layer(s) and metal nitride barrier layer (7) is applied and coated with gate metal layer (8). Between polysilicon layer and barrier layer is located metal contact film (6) preventing interaction between nitrogen in barrier layer and silicon in polysilicon layer. Barrier layer is chemically, thermally and mechanically stable layer on contact film. Independent claims are included for gate structure of transistor.
机译:半导体衬底(10)中的晶体管的栅极结构(1)通过结构化分层的栅电极叠层(1)而形成。在栅极介电膜(9)上沉积多晶硅层,并施加金属氮化物阻挡层(7)并用栅极金属层(8)涂覆。金属接触膜(6)位于多晶硅层和阻挡层之间,该金属接触膜(6)防止阻挡层中的氮与多晶硅层中的硅之间的相互作用。阻挡层是接触膜上的化学,热和机械稳定层。晶体管的栅极结构包括独立权利要求。

著录项

  • 公开/公告号DE102004004864A1

    专利类型

  • 公开/公告日2005-08-18

    原文格式PDF

  • 申请/专利权人 INFINEON TECHNOLOGIES AG;

    申请/专利号DE20041004864

  • 发明设计人 HAHN JENS;SCHMIDBAUER SVEN;BUERKE AXEL;

    申请日2004-01-30

  • 分类号H01L21/336;H01L29/78;

  • 国家 DE

  • 入库时间 2022-08-21 22:00:53

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