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Memory cell with improved data retention has memory layer, at least one bounding layer that is thicker towards lateral edges of channel region than in central region of channel region
Memory cell with improved data retention has memory layer, at least one bounding layer that is thicker towards lateral edges of channel region than in central region of channel region
The device has a semiconducting body (1) with an active region (2) in semiconducting material between lateral dielectric insulation regions (3), a channel region (4) in the active region, source/drain regions (5) at the ends of the channel region and a gate electrode (6) above it separated from the semiconducting material by a memory layer series (10) containing a memory layer (12) between bounding dielectric layers (11,13). At least one of the bounding layers is thicker towards the lateral edges (7) of the channel region than in a central region of the channel region.
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