Memory device, has mode control circuit to set operating mode based on received bit of multi-bit address signal selected by row or column decoder

摘要

A row decoder and a column decoder respectively select row and column of memory cell according to a multi-bit address signal. A mode control circuit sets an operating mode based on the received bit of multi-bit address signal which is selected by the row or column decoder. The operating mode is either a burst length mode or DLL reset mode or test mode or CAS latency mode or a burst type mode. Independent claims are also included for the following: (1) memory system; and (2) operating mode setting method for memory device.