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Phase-locked loop for communication between integrated circuit systems, has charge pump receiving control signals generated in response to comparison of reference clock signal and feedback signal

机译:用于集成电路系统之间通信的锁相环,电荷泵接收响应于参考时钟信号和反馈信号的比较而生成的控制信号

摘要

The loop (21) has a charge pump (22) receiving two control signals generated in response to a comparison of phases of a reference clock signal and a feedback signal. An operational amplifier with an input that receives a signal of the charge pump, and other two inputs receive the two control signals, respectively. A voltage controlled oscillator receives a control voltage signal and generates a feedback clock signal. Independent claims are also included for the following: (A) a memory system comprising a memory controller and memory modules with memory device (B) a method for receiving charge pump control signals.
机译:回路(21)具有电荷泵(22),电荷泵(22)接收响应于参考时钟信号和反馈信号的相位比较而产生的两个控制信号。运算放大器的输入端接收电荷泵的信号,其他两个输入端分别接收两个控制信号。压控振荡器接收控制电压信号并产生反馈时钟信号。还包括以下方面的独立权利要求:(A)包括存储器控制器和具有存储器设备的存储器模块的存储器系统(B)用于接收电荷泵控制信号的方法。

著录项

  • 公开/公告号DE102005017686A1

    专利类型

  • 公开/公告日2005-11-03

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号DE20051017686

  • 发明设计人 SOHN YOUNG-SOO;

    申请日2005-04-08

  • 分类号H03L7/10;G11C11/4193;G11C7/22;

  • 国家 DE

  • 入库时间 2022-08-21 22:00:36

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