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Ternary erase and read memory based on ternary and quaternary logic has pnp or or dual gate address decoder and four logic values
Ternary erase and read memory based on ternary and quaternary logic has pnp or or dual gate address decoder and four logic values
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机译:基于三元和四元逻辑的三元擦除和读取存储器具有pnp或双门地址解码器以及四个逻辑值
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摘要
A ternary erase and read memory (42) based on ternary and quaternary logic comprises an address decoder (44) after a PNP-logic OR-OR dual gate (9) whose output, controlled by two N-channel MOS transistors (V), passes to an end stage (17). Four different potential levels forming logic numbers 0,1,2,3 are applied to the gate.
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