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Ideal operational amplifier layout techniques for reducing the package-induced stress influence on offset voltage

机译:理想的运算放大器布局技术,可减少封装引起的应力对失调电压的影响

摘要

A method of reducing package stress includes placing matched components (A, B) of an op-amp substantially in a region of a die having the least stress gradients. The region is located in the centre (C) of the die. Further, the centre is the common centroid of the die. The matched components are the current mirror input stages of the op-amp. In one embodiment, a semiconductor configuration includes a die having a region with the least stress gradients, and an op amp containing matched components that are located substantially in the region.
机译:减少封装应力的方法包括将运算放大器的匹配组件(A,B)基本上放置在应力梯度最小的裸片区域中。该区域位于模具的中心(C)。此外,中心是模具的公共质心。匹配的组件是运算放大器的电流镜输入级。在一个实施例中,一种半导体配置包括:管芯,其具有应力梯度最小的区域;以及运算放大器,其包含基本上位于该区域中的匹配组件。

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