Noise reduction system for a dynamic random access memory device

摘要

A DRAM device comprises pluralities of bit and word lines, which could be arranged with at least one bit line on one metallization layer and other bit lines on other metallization layers, a memory cell 70 coupled to a first bit line 66 and a first word line 72, a reference cell 76 coupled to a second bit line 68 and a second word line 80, a differential sense amplifier 64 coupled to the first and second bit lines 66, 68, a controller to change a signal level on the first and second word lines 72, 80, during a read operation, which results in both activation of the memory and reference cells 70, 76 and noise being induced on the bit lines 66, 68. The DRAM device further comprises a noise reduction subsystem to inject a cancellation signal into the bit lines 66, 68. This subsystem comprises a first and second dummy cells 82, 84 coupled to the first and second bit lines 66, 68, and a control unit which deactivates the first and second dummy cells 82, 84 a short time prior to activation of the memory and reference cells 70, 76. The reference and second dummy cells 70, 76 share a common storage capacitor 90. The cancellation signal could be equal in magnitude and of opposite polarity to the noise.