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LAYOUT VERIFICATION METHOD, LAYOUT VERIFYING DEVICE, AND LAYOUT DESIGN DEVICE

机译:布局验证方法,布局验证设备和布局设计设备

摘要

PPROBLEM TO BE SOLVED: To enable it to verify a layout rule corresponding to working voltage only by using an actual process. PSOLUTION: Two or more layers are provided with circuit constituents for integrated circuits where two or more working voltages are used, and among the two or more layers, a specific layer is dissociated is arranged with high voltage circuit constituents so that each layer may recognize its working voltage so as to verify the layout by applying the working voltage according the working voltage. It is made possible to perform the layout verification by the layout rules according to the working voltage, without generating newly a dummy layer etc. , only by using a layer used on an actual process, and by recognizing the circuit constituents applied with which a high voltage on a layout. PCOPYRIGHT: (C)2007,JPO&INPIT
机译:

要解决的问题:仅使其通过实际过程即可验证与工作​​电压相对应的布局规则。

解决方案:两层或多层为使用两个或多个工作电压的集成电路提供了电路组件,并且在两层或更多层中,离解的特定层布置有高压电路组件,因此每一层可以识别其工作电压,以便通过根据工作电压施加工作电压来验证布局。仅通过使用在实际工艺中使用的层,并且通过识别施加了高电压的电路成分,就可以根据工作电压通过布局规则来进行布局验证,而无需新产生伪层等。布局上的电压。

版权:(C)2007,日本特许厅&INPIT

著录项

  • 公开/公告号JP2006286792A

    专利类型

  • 公开/公告日2006-10-19

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20050102718

  • 发明设计人 DEURA MANABU;

    申请日2005-03-31

  • 分类号H01L21/82;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 21:57:07

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