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PHYSICAL INFORMATION EXTRACTION REFLECTION METHOD, HIERARCHICAL CIRCUIT INFORMATION WITH PHYSICAL INFORMATION USING IT, AND CIRCUIT DESIGNING METHOD

机译:物理信息提取反射方法,使用该方法的带有物理信息的分层电路信息和电路设计方法

摘要

PPROBLEM TO BE SOLVED: To realize speeding up of circuit simulation and decrease of data quantity by reflecting in hierarchical circuit information the physical information extracted from layout information while maintaining a hierarchy structure, generating hierarchical circuit information with physical information, and thus reflecting to the circuit information of the hierarchical structure while maintaining accuracy. PSOLUTION: This method includes a physical information extraction process for extracting information regarding physical condition in a single unit such as element, cell, such as a parasitic element, a parasitic coupling element, a shape parameter of a device, and performance or property of the device, from layout information, or physical information and a physical information reflection process for reflecting the physical information to the circuit information consisting of hierarchy and acquiring the hierarchical circuit information while maintaining the hierarchical structure. PCOPYRIGHT: (C)2006,JPO&NCIPI
机译:

要解决的问题:通过在分级电路信息中反映从布局信息中提取的物理信息,同时保持分级结构,生成具有物理信息的分级电路信息,从而实现电路仿真的加速和数据量的减少,从而实现在保持准确性的同时,对层次结构的电路信息进行处理。

解决方案:此方法包括物理信息提取过程,用于提取有关单个单元(例如,寄生元件,寄生耦合元件,元件的形状参数,性能或从布局信息或物理信息获取设备的特性,以及用于将物理信息反映到由层次构成的电路信息并在保持层次结构的同时获取层次电路信息的物理信息反映过程。

版权:(C)2006,JPO&NCIPI

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