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BUS ADJUSTMENT METHOD AND BUS ADJUSTMENT DEVICE

机译:总线调整方法及总线调整装置

摘要

PROBLEM TO BE SOLVED: To solve the problem wherein it is difficult to execute bus adjustment while reflecting the importance of individual data transfer.;SOLUTION: A bus adjustment circuit 47 adjusts bus use requests issued from a plurality of bus masters. An address decode circuit 61 receives an access address signal issued from a bus master and outputs a data block the access of which is requested. A data transfer access priority setting table circuit 49 holds priority of each data block, and outputs the priority of the data block the access of which is requested on the basis of the output from the address decode circuit 16. A priority determination circuit 48 determines a bus master which requests the access to a data block having the highest priority on the basis of the output from the data transfer access priority setting table circuit 49, and permits the use of the bus to this bus master.;COPYRIGHT: (C)2006,JPO&NCIPI
机译:解决的问题:解决在反映单个数据传输的重要性的同时难以执行总线调节的问题。解决方案:总线调节电路47调节从多个总线主控器发出的总线使用请求。地址解码电路61接收从总线主机发出的访问地址信号,并输出请求访问的数据块。数据传输访问优先级设置表电路49保持每个数据块的优先级,并根据地址解码电路16的输出输出请求访问的数据块的优先级。优先级确定电路48确定一个总线主控器,根据数据传输访问优先级设置表电路49的输出请求访问具有最高优先级的数据块,并允许将该总线使用到该总线主控器。版权所有:(C)2006 ,JPO&NCIPI

著录项

  • 公开/公告号JP2006260230A

    专利类型

  • 公开/公告日2006-09-28

    原文格式PDF

  • 申请/专利权人 JAPAN RADIO CO LTD;

    申请/专利号JP20050077457

  • 发明设计人 OKAMURA TOSHIYUKI;KINOSHITA YUJI;

    申请日2005-03-17

  • 分类号G06F13/30;G06F13/18;

  • 国家 JP

  • 入库时间 2022-08-21 21:54:56

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