DELAY CALCULATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND CELL CHARACTERIZATION METHOD

摘要

PPROBLEM TO BE SOLVED: To solve the following problems of gate level delay calculation: input terminal capacity has drive load capacity and input through dependence, but the dependence thereof is not considered in delay calculation of a present situation, and the input terminal capacity is extracted more largely than apparent input terminal capacity. PSOLUTION: The input terminal capacity of a cell is previously found by a function expression, and the input terminal capacity is found in the delay calculation while calculating the input terminal capacity as a function of the drive load capacity and input through in each instance. In cell characterization, by finding a total of current flowing in an input terminal for a time until a voltage value of the input terminal arrives at a reference voltage, a value close to the actual apparent input terminal capacity can be found. PCOPYRIGHT: (C)2006,JPO&NCIPI