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Computational processing with fault recovery / fault tolerance

机译:具有故障恢复//容错能力的计算处理

摘要

A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204). IMAGE
机译:一种用于同步至少两个计算元件(CE1,CE2)的方法,每个计算元件具有与其他计算元件的时钟异步运行的时钟,该方法包括从由多个计算元件产生的一组信号中选择一个或多个称为元时间信号的信号。计算元件(CE1,CE2),监视计算元件(CE1,CE2)以检测其中一个计算元件(CE1)产生的选定信号,等待其他计算元件(CE2)产生选定信号,向每个计算元件发送等值的时间更新,并基于该时间更新来更新计算元件(CE1,CE2)的时钟。在本发明的第二方面中,通过将第一处理器指定为计算元件(204),将第二处理器(202)指定为控制器,连接计算元件(204)来制造容错或容错的计算机(200)。控制器(202)产生模块对,并连接至少两个模块对以产生故障容错或容错计算机(200)。计算机(200)的每个计算元件(202、204)以与其他计算元件(202、204)相同的周期数执行所有指令。该计算机系统包括一个或多个控制器(202)和至少两个计算元件(204)。 <图像>

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