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The differential output buffer, the difference input buffer, the semiconductor integrated circuit, and the circuit substrate

机译:差分输出缓冲器,差分输入缓冲器,半导体集成电路和电路基板

摘要

PPROBLEM TO BE SOLVED: To solve the problem that a differential input buffer, etc., malfunctions in receiving differential signals, if a cross-point potential deviates greatly from a reference voltage, and a detector circuit itself causes malfunction for a high operating frequency, even though a control trigger signal is checked in HH or LL detection. PSOLUTION: The differential output buffer 10 comprises a positive side output buffer 11P and a negative side output buffer 11N. Each output buffer has an output stage, a variable delay gate 114 and a fixed delay gate 115, to control the gates of transistors 112, 113 with outputs of the gates 114, 115. A differential input buffer block 20 comprises a differential input buffer 22 having inputs of a positive side signal and a reference voltage 31, a differential input buffer 23 having inputs of a negative side signal and the reference voltage, and a phase comparator 28 for making a control clock and data from the comparison result, to increase the delay in the variable delay gate 114 and set a cross point voltage to the reference voltage. PCOPYRIGHT: (C)2004,JPO
机译:

要解决的问题:如果交叉点电势与参考电压有很大偏差,并且检测器电路本身引起高电平故障,则解决差分输入缓冲器等在接收差分信号时出现故障的问题。即使在HH或LL检测中检查了控制触发信号,也无法达到工作频率。

解决方案:差分输出缓冲器10包括正侧输出缓冲器11P和负侧输出缓冲器11N。每个输出缓冲器具有输出级,可变延迟门114和固定延迟门115,以利用门114、115的输出来控制晶体管112、113的栅极。差分输入缓冲器块20包括差分输入缓冲器22。具有正侧信号和参考电压的输入端31,具有负侧信号和参考电压的输入的差分输入缓冲器23以及用于根据比较结果制成控制时钟和数据的相位比较器28延迟可变延迟门114中的延迟,并将交叉点电压设置为参考电压。

版权:(C)2004,日本特许厅

著录项

  • 公开/公告号JP3794347B2

    专利类型

  • 公开/公告日2006-07-05

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP20020155245

  • 发明设计人 泊 史朗;

    申请日2002-05-29

  • 分类号H03K19/0175;H03F1/56;H03K5/135;

  • 国家 JP

  • 入库时间 2022-08-21 21:49:19

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