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How high-speed data transfer synchronization system and high-speed data transfer synchronization
How high-speed data transfer synchronization system and high-speed data transfer synchronization
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机译:高速数据传输同步系统如何与高速数据传输同步
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摘要
One memory controller and a plurality of memory modules are connected to a data bus line, clock bus line, and command bus line. Each memory module includes an internal clock signal generating circuit for generating internal clocks synchronizing with external clock signals output from the memory controller. This internal clock signal generating circuit has a function of adjusting the timing of a generated internal clock signal on the basis of a control signal in accordance with the position on the bus lines of a memory module having this internal clock signal generating circuit.
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