System for optimizing method, and a memory access time in a computer to optimize the transfer of data between the system memory and a PCI master device

摘要

PURPOSE: To provide a system for optimizing data transfer time between an external master device and a main memory. ;CONSTITUTION: The system includes an integrated processor provided with a PCT bridge 80 for adjusting data transfer to/from a PCT master 75 and a memory controller 90 for controlling an access to the main memory. When the PCI master 75 can not timely respond, the bridge 80 asserts a MEMWAIT signal to the controller 90 to indicate the necessity of deceleration of data transfer, applies a succeeding memory address to open a proper page in the memory and asserts a suitable row address strobe line to accelerate succeeding data transfer. When the MEMWAIT signal is deasserted, the controller 90 immediately asserts a column address strobe line to drive data. Since the page in the memory is quickly opened, RAS access time and RAS precharging time can be saved.;COPYRIGHT: (C)1997,JPO