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DSP processor architecture with write Datapath word conditioning and analysis
DSP processor architecture with write Datapath word conditioning and analysis
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机译:具有写数据路径字调节和分析功能的DSP处理器架构
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摘要
An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving word conditioning operations from the critical path to the write datapath, the throughput of common DSP functional blocks such as multiplier-accumulator (MAC) blocks may be improved. Delays may be further reduced by combining analysis operations with write or move operations.
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