BODY-BIASED ENHANCED PRECISION CURRENT MIRROR

摘要

A body-biased enhanced current mirror reference circuit is disclosed wherein the body bias voltage of a current mirror device is varied to adjust its threshold voltage. Both the drain and body potentials of a replica mirror transistor are controlled to selected values. The drain is set to an expected DC voltage output of an NFET current mirror device. The body potential is set to a maximum desired value to prevent forward biasing of the body-to-diffusion junction(s) of one or more current mirror devices, which is accomplished by a feedback control circuit. A low-frequency, low-precision op amp drives the gate of a replica load device so that the body of the replica NFET current mirror device is set to a maximum bias voltage. The maximum bias voltage is also used to bias the body of a diode connected NMOS reference transistor, so that the current in the NFET current mirror device will be approximately equal to the current in the diode-connected NMOS reference. An auxiliary NFET current mirror device may be added to the body-biased enhanced current mirror circuit with the body connected to ground as in the unmodified current mirror to negate a non-monotonicity of the current output.