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System and method for verifying trace lengths and trace spaces in a circuit
System and method for verifying trace lengths and trace spaces in a circuit
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机译:用于验证电路中的迹线长度和迹线空间的系统和方法
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摘要
The present invention provides a method for verifying trace lengths and trace spaces in a circuit. The method includes the steps of: retrieving information of a trace layout of the circuit; retrieving preset design rules on the trace lengths and the trace spaces of the trace layout; computing trace lengths and trace spaces of traces in the trace layout; verifying trace lengths and trace spaces in the trace layout by comparing the computed trace lengths and trace spaces of the traces with the preset design rules; and reporting results of the verifying step. A related system is also provided.
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