Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices

摘要

Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or sub-microscale address lines. A greater number of address lines than a minimal number of address lines needed for unique addressing in a deterministic, non-randomly fabricated multiplexer or demultiplexer are used. The number of address lines in excess of the minimal number of address lines needed for unique addressing in a deterministic multiplexer or demultiplexer are referred to as supplemental address lines. The number of supplemental address lines needed for a randomly fabricated nanoscale multiplexer or demultiplexer can be decreased by employing two stages within the multiplexer or demultiplexer, the first stage having deterministically fabricated interconnections between signal lines and a first set of address lines, and the second stage having randomly fabricated interconnections between signal lines and a second set of address lines.