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Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates
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机译:通过在复杂的动态多米诺骨牌CMOS栅极中应用固有并行性来减少电荷共享
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摘要
The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
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