A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and second inputs, a select line input, and a carry/borrow output. The carry circuit also includes an AND gate, an OR gate and an XOR gate. The AND gate has two inputs, and an output connected to the first input of the first multiplexer. The OR gate has two inputs, and an output connected to the second input of the first multiplexer. The XOR gate has a first input, and an output connected to the select line input of the first multiplexer. A second multiplexer has an output connected to the first input of the XOR gate. The at least one LUT and the at least one carry circuit provides independent sum and carry outputs for different function requirements.
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