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Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
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机译:使用紧凑的低功耗延迟锁定环(DLL)合成时钟信号的方法和装置
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摘要
A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. Also, a set of phase-delayed clock signals is generated in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. Further, the set of phase-delayed clock signals is combined to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.
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