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Method of manufacturing a semiconductor integrated circuit device including a hole formed in an insulating film and a first conductive film formed over a bottom region and sidewalls of the hole

机译:制造包括在绝缘膜中形成的孔和在该孔的底部区域和侧壁上方形成的第一导电膜的半导体集成电路器件的制造方法

摘要

In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
机译:在制造半导体集成电路器件时,在形成在半导体衬底上的第一层互连之上的层间绝缘膜中形成互连沟槽和接触孔,在沟槽和接触孔的内部形成阻挡膜,使得其膜从孔的底部的中心到围绕接触孔的底部的整个侧壁的厚度增加,在阻挡膜上形成铜膜,并通过抛光形成第二级互连和连接器部分(插头)由CMP。这样,从第二级互连通过连接器部分(插头)流向第一级互连的电流的几何最短路径与具有最低电阻的薄阻挡膜部分不一致,因此电流路径可以分散,电子的聚集不容易发生。

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