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Methods and apparatus for improving critical path analysis using gate delay
Methods and apparatus for improving critical path analysis using gate delay
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机译:利用门延迟来改善关键路径分析的方法和装置
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摘要
Disclosed are novel methods and apparatus for efficiently providing critical path analysis of a design. In an embodiment, an apparatus disclosed can assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and one simulation is required instead of the two generally required.
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