首页> 外国专利> Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip

Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip

机译:将相加和相减形成的导电迹线和绝缘基底连接到半导体芯片的方法

摘要

A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a metal base, an insulative base, a routing line and an interconnect, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the routing line is disposed on a side of the insulative base that faces towards the chip, and the interconnect extends through a via in the insulative base and electrically connects the metal base and the routing line, forming an opening that extends through the insulative base and exposes the pad, forming a connection joint that electrically connects the routing line and the pad, and etching the metal base such that an unetched portion of the metal base forms a pillar that overlaps and is aligned with the via and contacts the interconnect, wherein a conductive trace includes the routing line, the interconnect and the pillar. Preferably, the opening extends through an insulative adhesive that attaches the routing line to the chip.
机译:一种将导电迹线和绝缘基底连接到半导体芯片的方法,包括提供半导体芯片,金属基底,绝缘基底,布线和互连,其中,芯片包括导电焊盘,金属基底设置在其上所述绝缘基底的背离所述芯片的一侧,所述布线设置在所述绝缘基底的面向所述芯片的一侧上,并且所述互连延伸穿过所述绝缘基底中的通孔,并且将所述金属基底与所述金属基底电连接。布线,形成延伸穿过绝缘基底并暴露焊盘的开口,形成将布线和焊盘电连接的连接接头,并对金属基底进行蚀刻,以使金属基底的未蚀刻部分形成一个重叠的支柱并与通孔对准并接触互连,其中导电迹线包括布线,互连和柱。优选地,该开口延伸穿过将路线连接至芯片的绝缘粘合剂。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号