CACHE UPDATE METHOD AND CACHE UPDATE CONTROL SYSTEM EMPLOYING NON-BLOCKING TYPE CACHE

摘要

If a cache miss occurs at a time of a loadrequest from a processor core, an issuance check block(20) issues a request of reading out data caused bythe cache miss, to a main memory from an issuancecontrol circuit (50), and then registers theinformation of the request in a request buffer circuit(30). A cache block (10) does not update an addressarray (12) at that time, and it is processed as acache hit if a following instruction is hit to anaddress stored in an entry of an update schedule. Theupdate of the address array (12) is donesimultaneously with the update of a data array (11)when responsive data is received from the main memorywith regard to said request. Accordingly, it ispossible to provide a new cache update method, inwhich the feature of a cache of a non-blocking typecan be sufficiently used, such as the merit ofcontinuing a process for a following instruction evenwhile the request of reading out the data caused bythe cache miss is sent to the main memory.