The invention provides circuits (404, 405) that are tolerant to soft errors, such as a single event upset (SEU). The circuits (404, 405) may have a chain of permitted state changes. Redundant elements, including redundant literals and assignments, are designed and implemented in the circuit. The design is such that a disruption or change of state on a single element by and SEU will not change the state flow of a circuit or lead to impermissible state changes. In one embodiment, the invention is implemented in quasi-delay- insensitive (QDI) asynchronous circuits.
展开▼