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LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
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机译:LVDS接口结合了用于可编程逻辑器件的锁相环电路
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摘要
An LVDS interface for a programmable logic device uses phase-locked loop ("PLL") circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.
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