DIGITAL CLOCK MULTIPLIER AND DIVIDER WITH SYNCHRONIZATION

摘要

A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clock signal multiplied by a multiplier M and divided by a divisor D. In one embodiment of the present invention, the average frequency of the output clock signal during a concurrence period is equal to the selected frequency because the active edge of the output clock signal is triggered by the rising edge of the reference clock signal during a concurrence. Furthermore, the waveform of the output clock signal is shaped to approximate the waveform of an ideal output clock signal by selectively inserting delays distributed throughout the concurrence period using a Modulo-M delta sigma circuit. The modulo-M delta sigma circuit, which receives modulo value M, a pulse value P, and a clock signal, generates an output signal that includes P pulses spread across M clock periods.