Methods (300,350) are disclosed for fabricating shallow isolation trenches and structures in multi- bit SONOS flash memory devices. One method aspect (300) comprises forming (310) a multi-layer dielectric-charge trapping-dielectric stack (420) over a substrate (408) of the wafer (402), for example, an ONO stack (420), removing (312) the multi-layer dielectric-charge trapping-dielectric stack (420) in a periphery region (406) of the wafer (402), thereby defining a multi-layer dielectric-charge trapping- dielectric stack (420) in a core region (404) of the wafer (402). The method (300) further comprises forming (314) a gate dielectric layer (426) over the periphery region (406) of the substrate (408), forming (316) a first polysilicon layer (428) over the multi-layer dielectric-charge trapping-dielectric stack (420) in the core region (402) and the gate dielectric (426) in the periphery region (406), then concurrently forming (318) an isolation trench (438) in the substrate (408) in the core region (404) and in the periphery region (406). Thereafter, the isolation trenches are filled (326) with a dielectric material (446), and a second polysilicon layer (452) that is formed (332) over the first polysilicon layer (428) and the filled trenches (438), forming an self-aligned STI structure (446). The method (300) avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.
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