Low power pipeline domino logic disclosed herein comprises a plurality of logic blocks that operate in succession, depending on the connection order, and each logic block in response to a logic evaluation activation signals generated from the logic block is connected to the previous stage performs a logical evaluation and it generates a new logical assessment activation signal for activating the logical evaluation of the logic blocks connected to the next stage. Since logical assessment activation signal generated from each of the logic blocks is not sharing a clock signal, without being affected by the cycle of the clock, and can guarantee fully the next stage of the logic evaluation point, whereby a multi-stage domino logic circuit such as a decoder it is not necessary to connect a latch circuit, a sense amplifier circuit between the logic blocks to implement, it is possible to reduce the power consumption, it is possible to reduce the area occupied by the circuit.
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