SYSTEM ON CHIP(SOC) ARCHITECTURE WITH CPU

摘要

This invention is a system bus of the optimized SOC to prevent the degradation of the SOC in developing SOC intended to provide a structure with a built-in CPU SOC having the structure , ARM CPU having a plurality of the internal data bus , and peripheral data bus function block having less than the internal CPU, the internal CPU and the respective peripheral function block multi-layer bus matrix system bus (Multi Layer Bus Matrix) and bus connections to the matrix structure , downsized module that converts the bit -band ARM master data bus of the internal CPU data bus as a slave peripheral functional blocks of the band (Downsizer Module:. it consists of including DS) and