SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE WITH INPUT-DATA CONTROLLER OF HAVING ADVANTAGE IN TERMS OF LOW POWER AND HIGH FREQUENCY

摘要

The present invention is a data input unit simpler than the prior art for receiving the data transmitted to the internal memory cell blocks, while suitable for high frequency and that for providing a synchronous memory device is configured to reduce the power consumption, the invention To this end, the write command to receive the synchronization data which is input in response to the clock signal input continuously align the number of data inputted in parallel by a free number the patch data through the one data input pin of the outputs of a plurality of aligned data, data alignment workers; Data input in response to a strobe signal, a global input and output lines for outputting the plurality of aligned data to the memory core region by selecting an even number data or the odd-numbered data driver; Data input strobe signal generating unit for buffering the clock signal output by the input data strobe signal; And a synchronous memory device having a data input strobe signal control part for outputting the data input strobe control signal for controlling the generation the data input strobe signals so that only the said data input strobe signal output interval operation takes place corresponding to the write command It provides. ; Memory, data alignment, data strobe signal, rising, polling.