Delay modeling circuit for controlling locking time of DLLDelay Locked Loop in semiconductor device using double power supply

摘要

PURPOSE: A delay modeling circuit of a DDL is provided to secure an exact phase fixing time of a delay fixing loop under first and second power supplies which electric potential are different, and a stable data outputting operation of a semiconductor memory device using first and second power supplies and providing a delay fixing loop. CONSTITUTION: A delay modeling circuit includes first and second power supplies(VDD1,VSS1,VDD2,VSS2), first and second delay modeling portions(100,110), and a noise filtering portion(120). The first power supply is a power supply of the core portion of a semiconductor memory device. The first delay modeling portion is inputted the first power supply and models the total delay time in the core portion for reading and outputting a data stored to the semiconductor memory device. The second power supply maintains an electric potential different from the first power supply and is a power supply of the interface portion of the semiconductor memory device. The noise filtering portion is inputted the second power supply and removes noise of the interface portion. The second delay modeling portion is inputted the second power supply filtered by the noise filtering portion and models the total delay time in the interface portion for driving the data toward the outside.