首页> 外国专利> Boosting circuit and multi-stage boosting circuit using the same

Boosting circuit and multi-stage boosting circuit using the same

机译:升压电路及使用该升压电路的多级升压电路

摘要

The city implemented as an integrated circuit layout area smaller and also to remove the threshold voltage of the transistors in the final boost voltage loss The number in the step-up circuit and a multi-stage step-up circuit using the same are disclosed. The step-up circuit includes a first input terminal, between the first input and a second input of opposite phase, that the connection is established, the capacitor to the first input terminal, an output terminal that is connected to the other terminal of the capacitor, the output terminal and the reference voltage terminal a first MOS transistor being connected, between the gate and the gate is connected between the first input terminal of the first MOS transistor and a second MOS transistor coupled to said reference voltage terminal, and the gate and the output terminal of said first MOS transistor connecting a gate characterized by a third MOS transistor connected to the second input. Wherein the reference voltage corresponds to the supply voltage terminal stage. Wherein the first MOS transistor and the third MOS transistor is a PMOS transistor, the second MOS transistor is an NMOS transistor.
机译:该城市被实现为更小的集成电路布图面积,并且还去除了最终升压电压损失中的晶体管的阈值电压。公开了升压电路中的数目和使用该升压电路的多级升压电路。升压电路包括第一输入端子,该第一输入端子在第一输入和反相的第二输入之间,该第一输入端子与该第二端子建立连接,电容器连接至第一输入端子,输出端子连接至电容器的另一端子。所述输出端和所述参考电压端之间连接有第一MOS晶体管,所述栅极和所述栅极之间连接在所述第一MOS晶体管的第一输入端和耦合至所述参考电压端的第二MOS晶体管之间,以及所述第一MOS晶体管的输出端子连接栅极,所述栅极的特征在于,第三MOS晶体管连接到第二输入。其中参考电压对应于电源电压端子级。其中,第一MOS晶体管和第三MOS晶体管为PMOS晶体管,第二MOS晶体管为NMOS晶体管。

著录项

  • 公开/公告号KR100594286B1

    专利类型

  • 公开/公告日2006-06-30

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20040051806

  • 发明设计人 이현석;유형식;

    申请日2004-07-03

  • 分类号G11C5/14;

  • 国家 KR

  • 入库时间 2022-08-21 21:23:31

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