equivalent circuit modeling method for clock skew analysis of multi-driven clock grid network

摘要

PURPOSE: An equivalent circuit modeling method is provided to accurately estimate a delay time of a multiplex driving clock grid circuit and analyze a clock skew by considering an influence of a parasitic component, and by rapidly analyzing timing, electric power and signal integrity. CONSTITUTION: A two-dimensional table is automatically generated for estimating an input transition delay, a cell delay and an output transition delay using a standard parasite format file(30). An effective capacitance corresponding to each driver is estimated. An equivalent circuit of the effective capacitance is generated(32). The cell delay and the output transition delay of each driver are estimated using the two-dimensional table(34). An effective resistance of each driver is estimated. A single resistor voltage ramp model is generated as the standard parasite format file(36). A radio wave delay and a transition delay of each loading terminal of the single resistor voltage ramp model are estimated(38). An arriving time and a transition delay up to each loading terminal are estimated. A clock skew is estimated(40). The arriving time, the transition delay and the clock skew are displayed(42).