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Non-volatile memory cell array e.g. 4F2 memory cell array, has cells formed by transistors, where source/drain connection of each transistor of two columns is connected with electrical conductor in respective metallization levels
Non-volatile memory cell array e.g. 4F2 memory cell array, has cells formed by transistors, where source/drain connection of each transistor of two columns is connected with electrical conductor in respective metallization levels
The array has non-volatile memory cells, each formed by a memory transistor. The transistors are arranged in a matrix with several rows and columns (405, 406). Source/drain connection of each transistor of one column is connected with an electrical conductor in a metallization level. Source/drain connection of each transistor of another column is connected with another conductor in another level, which is not equal to the former level. The non-volatile memory cells stores electrical charge carriers in a non-volatile manner. The latter transistor column is adjacent to the former transistor column.
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