首页> 外国专利> Package structure, e.g. flip chip ball grid array package, includes substrate having conductive lines, solder bumps, patterned elastic dielectric layers, and conductive layer to form zigzag conductive layer pattern

Package structure, e.g. flip chip ball grid array package, includes substrate having conductive lines, solder bumps, patterned elastic dielectric layers, and conductive layer to form zigzag conductive layer pattern

机译:包装结构,例如倒装芯片球栅阵列封装,包括具有导线,焊料凸块,图案化的弹性介电层和形成锯齿形导电层图案的导电层的基板

摘要

A package structure comprises a substrate having conductive lines, solder bumps (A13), a patterned first elastic dielectric layer, a conductive layer to form a zigzag conductive layer pattern, and a second elastic dielectric layer having openings including solder bumps. A package structure comprises: (1) a substrate having conductive lines; (2) solder bumps electrically coupling with the conductive lines; (3) a patterned first elastic dielectric layer covering a partial region of a passivation layer formed on chips; (4) a conductive layer formed on the patterned first elastic dielectric layer to form a zigzag conductive layer pattern due to the topography of the patterned first elastic dielectric layer, where the zigzag conductive layer pattern is partially attached on the passivation layer and partially attached on the first elastic dielectric layer; and (5) a second elastic dielectric layer covering the conductive layer, the second elastic dielectric layer having openings, each of the openings having solder bumps electrically coupling with one of the conductive lines. An independent claim is also included for a conductive bumping arrangement for a package, comprising: (1) bonding pads formed on a die; and (2) bumpings formed over the die and connected to the bonding pads by conductive traces, where an included angle between a line segment from center (C1) of the die to center (C2) of the bumping and a radius orientation from the center of the bumping of the conductive traces departing from the bumping is greater than 45[deg].
机译:封装结构包括:具有导电线的基板,焊料凸块(A13),图案化的第一弹性电介质层,形成锯齿形的导电层图案的导电层,以及具有包括焊料凸块的开口的第二弹性电介质层。一种封装结构,包括:(1)具有导线的基板;以及(2)与导电线电耦合的焊料凸点; (3)图案化的第一弹性介电层,其覆盖形成在芯片上的钝化层的部分区域; (4)由于图案化的第一弹性电介质层的形貌而在图案化的第一弹性电介质层上形成以形成锯齿状的导电层图形的导电层,其中该字形的导电层图形部分地附着在钝化层上并且部分地附着在钝化层上。第一弹性介电层; (5)覆盖导电层的第二弹性电介质层,第二弹性电介质层具有开口,每个开口具有与导电线之一电耦合的焊料凸块。还涉及一种用于包装的导电凸点装置的独立权利要求,其包括:(1)形成在管芯上的焊盘;以及(2)凸块形成在裸片上并通过导电迹线连接到接合垫,其中,从裸片的中心(C1)到凸块的中心(C2)的线段与该中心的半径方向之间的夹角偏离凸点的导电迹线的凸点的角度大于45°。

著录项

  • 公开/公告号DE102004061876A1

    专利类型

  • 公开/公告日2006-06-01

    原文格式PDF

  • 申请/专利权人 ADVANCED CHIP ENGINEERING TECHNOLOGY INC.;

    申请/专利号DE20041061876

  • 发明设计人 YANG WEN-KHUN;

    申请日2004-12-22

  • 分类号H01L23/50;H01L23/498;

  • 国家 DE

  • 入库时间 2022-08-21 21:20:33

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