Trinary full subtracter circuit for digital computers has half-adder and half-subtracter with OR gate interconnected for generation of output whereby different potential levels are represented by different logical numbers

摘要

The circuit for trinary full subtracter (38) has a half-adder (34) and a half-subtracter (35) with an OR gate (5) interconnected for the generation of output. Four different electric potential levels are represented by four different logical numbers. The half-adder is made up of one PNP logical AND-AND dual gate (10) and a OR-OR dual gate (9) and the half-subtracter consists of two PNP logical OR-OR gates.