The process involves detecting a length in relevant bits of a bi-phase asynchronous frame to decode the frame, where the length of the frame varies from one frame to another frame. A functioning mode e.g. normal mode and test mode, of an electronic circuit is selected based on the detected length. The electronic circuit is processed as test frame after detecting the length of the frame, when a test mode is selected. Independent claims are also included for the following: (A) a computer program product having instructions for executing a process of decoding bi-phase asynchronous frame (B) a storage unit having instructions executable by a computer for implementing a process of decoding bi-phase asynchronous frame (C) a control device including an electronic circuit for decoding a bi-phase asynchronous frame.
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