Integrated memory circuit e.g. static RAM memory, has memory cell columns whose bit lines are formed as two partial bit lines, and memory cells implemented as group of cells connected to partial bit lines

摘要

The circuit has a memory cell matrix arranged as rows and columns between two bit lines (BL0, BL1, BLB0, BLB1) via access transistors (T, T`). Each bit line of the column maintained at high pre-charge potential is formed as two partial bit lines (BL01, BL02, BL11, BL12). Memory cells of each column are implemented as a group of cells connected to the partial bit lines. An independent claim is also included for a method for fabricating an integrated memory circuit.