首页> 外国专利> A circuit for maintaining hold-up time while reducing bulk capacitor size and improving efficiency in a power supply

A circuit for maintaining hold-up time while reducing bulk capacitor size and improving efficiency in a power supply

机译:一种用于保持保持时间,同时减小大容量电容器尺寸并提高电源效率的电路

摘要

A circuit that utilizes most of the energy stored in the bulk capacitor of an AC to DC or DC to DC converter power supply by providing an intermediate converter between a first stage boost converter and a DC-DC converter. When the bulk voltage starts to fall during the hold-up time, the intermediate converter boosts the falling voltage to maintain the regulated DC input to the DC to DC converter while reducing the operating range and increasing the operating duty cycle, so as to increase efficiency, reduce peak current and voltage stresses, reduce the size of output filter components and reduce the size of the bulk capacitance by up to half.
机译:通过在第一级升压转换器和DC-DC转换器之间提供中间转换器来利用存储在AC-DC或DC-DC转换器电源的大容量电容器中的大部分能量的电路。当在保持时间内大电压开始下降时,中间转换器会提高下降电压,以保持稳定的直流输入到直流到直流转换器,同时减小工作范围并增加工作占空比,从而提高效率,降低峰值电流和电压应力,减小输出滤波器组件的尺寸并将体积电容的尺寸减小多达一半。

著录项

  • 公开/公告号GB2420666A

    专利类型

  • 公开/公告日2006-05-31

    原文格式PDF

  • 申请/专利权人 ASTEC INTERNATIONAL LIMITED;

    申请/专利号GB20060001296

  • 发明设计人 VIJAY PHADKE;

    申请日2004-08-06

  • 分类号H02M1;H02M1/42;H02M3/28;

  • 国家 GB

  • 入库时间 2022-08-21 21:16:30

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号