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FAILURE ANALYSIS PROGRAM, RECORDING MEDIUM WITH PROGRAM RECORDED THEREON, FAILURE ANALYSIS METHOD, AND FAILURE ANALYSIS DEVICE

机译:故障分析程序,将程序记录到其中的记录介质,故障分析方法以及故障分析装置

摘要

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor integrated circuit and shortening its manufacturing period of time.;SOLUTION: Failure analysis device 1100 extracts a partial path containing a failure part from among paths in a circuit to be analyzed by a partial path extraction section 1101, then detects an expansion path from a circuit element at a front stage of a start point of the extracted partial path via the partial path to a circuit element at a rear stage of an end point of the partial path by a path detection section 1102, extracts the shortest expansion path from among a group of the expansion paths by an expansion path extraction section 1103, determines whether the path length of the expansion path is longer than a prescribed reference length by a determination section 1104, and determines the expansion path as a path to be used in failure simulation by a decision section on the basis of the decision results determined by the determination section 1104.;COPYRIGHT: (C)2008,JPO&INPIT
机译:解决的问题:为了提高半导体集成电路的可靠性并缩短其制造时间。解决方案:故障分析装置1100通过部分路径提取从要分析的电路中提取包含故障部分的部分路径。然后,通过路径检测部检测从所提取的局部路径的起点的前段的电路元件经由局部路径到局部路径的终点的后段的电路元件的展开路径。 1102,由扩展路径提取部分1103从一组扩展路径中提取最短的扩展路径,由确定部分1104确定扩展路径的路径长度是否长于规定的参考长度,并确定扩展路径作为确定部分1104确定的确定结果的基础上,确定部分在故障模拟中使用的路径。著作权:(C)2008,JPO&INPIT

著录项

  • 公开/公告号JP2007271290A

    专利类型

  • 公开/公告日2007-10-18

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20060093822

  • 发明设计人 HIRAIDE TAKAHISA;

    申请日2006-03-30

  • 分类号G01R31/28;

  • 国家 JP

  • 入库时间 2022-08-21 21:16:08

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