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Correction techniques and overlay metrology of the layers for the IC fabrication
Correction techniques and overlay metrology of the layers for the IC fabrication
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机译:集成电路制造层的校正技术和覆盖层计量
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摘要
System that facilitates measurement and correction of overlay error between multiple layers of the wafer (402) is disclosed. Determining overlay targets representing the overlay of layers of more than two wafers (402) and (406), the overlay errors present in the (406) overlay target, as a result, the system, three or more wafer (402) I and a (408) measurement component for determining the overlay error between the layers. Between adjacent layers, and, in order to correct overlay error between the layers that are not adjacent, well, this correction measurements (408) acquires the measurement component is at least partially control component (410) is provided I based on.
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