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INTERCONNECT COMMUNICATION PACKAGING ERROR-CORRECTING FUNCTION WITHOUT AFFECTING LATENCY IN CASE OF NO ERROR

机译:互连通信打包错误纠正功能,在不出现错误的情况下不影响延迟

摘要

PPROBLEM TO BE SOLVED: To achieve interconnect communication mounting an error-correcting function without affecting latency when there occurs no error in a reception apparatus (600) that transfers an output from a transmission apparatus (500) through an external communication path (530) to a next-stage processing circuit (700) connected to the next stage. PSOLUTION: The reception apparatus comprises: a circuit (610) for receiving an input of a reception packet and detecting a portion corresponding to a header; an Invalidation generation circuit (623) which decodes the reception packet, performs error detection and generates an Invalidation signal if any error is detected; a decoding circuit (620) including a buffer (621) capable of holding that reception packet just for a time required for error correction; and an output selection circuit (630) for selecting, using the Invalidation signal, whether to turn the reception packet into a state of speculatively transferring the reception packet to a next-stage processing circuit on the next stage while keeping it as it is without ending reception of the reception packet, or to turn the reception packet into a state of transferring the reception packet after decoding. PCOPYRIGHT: (C)2007,JPO&INPIT
机译:

要解决的问题:当在通过外部通信路径从传输设备(500)传输输出的接收设备(600)中没有发生错误时,为了实现互连通信安装了纠错功能而不影响等待时间,互连通信( 530)连接到下一级的下一级处理电路(700)。解决方案:接收设备包括:电路(610),用于接收接收分组的输入并检测与报头相对应的部分;以及无效产生电路(623),对接收分组进行解码,进行错误检测,如果检测到任何错误,则产生无效信号;解码电路(620)包括缓冲器(621),该缓冲器能够仅在纠错所需的时间内保持该接收分组;输出选择电路(630),其使用无效信号选择是否将接收包转换为将接收包推测性地传送到下一阶段的下一阶段处理电路的状态,同时保持其原样而不结束。接收包的接收,或者将接收包转换为解码后传输接收包的状态。

版权:(C)2007,日本特许厅&INPIT

著录项

  • 公开/公告号JP2007104460A

    专利类型

  • 公开/公告日2007-04-19

    原文格式PDF

  • 申请/专利权人 INTERNATL BUSINESS MACH CORP IBM;

    申请/专利号JP20050293310

  • 发明设计人 KATAYAMA YASUNAO;

    申请日2005-10-06

  • 分类号H04L1/00;G06F11/10;

  • 国家 JP

  • 入库时间 2022-08-21 21:12:31

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