Buffer control system and buffer controllable memory

摘要

A buffer control system and a buffer controllable memory are provided that remedy the problem of increased current consumption at a time of lower clock speed. A buffer control system 10 includes a processor 100 for outputting a memory control signal 500 that determines its on/off time depending upon the clock speed, and an operation mode switching signal 800 that indicates either a high-speed operation mode or low-speed operation mode. An external memory 200, connected to the processor 100, sends and receives data, and has a bus buffer 210 whose on/off time is determined according to a memory control signal 600 input thereto. A buffer controller 900, connected between the processor 100 and external memory 200, contains a timer 400 triggered by the memory control signal 500 from the processor 100. The buffer controller 900 reduces the width of the memory control signal input from the processor for a predetermined time determined by the timer before outputting it to the external memory 200, when the operation mode switching signal 800 input thereto indicates the low-speed mode.